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this optimization will reduce routing delays but will increase area. This optimization may cause inferior results if the utilization of the device is already high. If the placement tool is not intelligent enough to only perform this on critical-path routes, this option may need to be disabled and duplication added to the RTL with corresponding don t touch attributes to ensure that the synthesis does not optimize the duplicate structures.

Optimizing across hierarchical boundaries will allow any of the placement algorithms to operate when the path extends across a module boundary as shown in Figure 16.6. Typically, if a particular optimization is desired, it will be bene cial to apply it to intermodule interfaces as well as simply the paths within the modules themselves. Often, logic at the module boundaries does not fully occupy entire LUTs. An example is shown in Figure 16.7. In this above, a separate LUT is used to implement a NAND operation at each module boundary. By enabling the optimization across boundaries, each of these logical operations can be combined into a single LUT, thereby reducing the area utilization of this operation by one half. The primary case where this would not be desired is if gate-level simulations need to be run on the postimplementation netlist. In this case, a hierarchy that is intact will be very desirable.

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when others=>--"1111" and 0100 to 1010 q _ pos<= 0 ; q _ neg<= 0 ; en<= 0 ; op<= - ; end case; end process; end behavioral;

Volatility Analysis (standard deviation relative to all funds)

If debug is required on the back-annotated netlist, a preserved hierarchy will allow the designer not only to traverse the design but also to easily identify signals at the boundaries of the modules that may be useful for debug.

The divider structure is:

(Oct '92 Dec '92) (Sep '00 Nov '00)

Many FPGAs have ip- ops built into the input and output buffers to optimize the timing in and out of the chip. Along with these special I/O buffers will be an optimization to enable or disable the packing of these registers into the I/O. Figure 16.8 illustrates the concept of packing registers into the I/O buffers. There are a number of advantages to placing a register in the I/O:

entity srt_carry_save_r2 is port ( X: in std_logic_vector (N downto 0); Y: in std_logic_vector (N-1 downto 0); Q: out std_logic_vector (P downto 0); R: out std_logic_vector (N downto 0) ); end srt_carry_save_r2; architecture rtl of srt_carry_save_r2 is type rems is array (0 to P) of std_logic_vector (N+2 downto 0); signal c, s, c_o, s_o: rems; signal q _ pos, q _ neg, en, op: std_logic_vector (P-1 downto 0); signal qq: std_logic_vector (P downto 0); signal rr: std_logic_vector (N+1 downto 0); begin s(0)<=X(N)&X& 0 ; c(0)<=(others=> 0 ); gen _ p: for i in 0 to P-1 generate selc: srt_cs_selection port map(s(i)(N+2 downto N-1), c(i)(N+2 downto N-1), en(P-i-1), op(P-i-1), q _ pos(P-i-1), q _ neg(P-i-1)); cell: srt_cs_cell port map (Y, c(i)(N+1 downto 0), s(i)(N+1 downto 0), en(P-i-1), op(P-i-1), c_o(i)(N+1 downto 0), s_o(i)(N+1 downto 0)); c(i+1)<=c_o(i)(N+1 downto 0)& 0 ; s(i+1)<=s_o(i)(N+1 downto 0)& 0 ; end generate; rr<=c(P)+s(P); qq<=( 0 &q_pos) - q_neg; nal_adjust: correction_cell port map (QQ, rr(N+1 downto 1), Y, X(N), rr(N+1), Q, R); end rtl;

27 08% 16 67%

. . . .

Comment 13.2 The circuit of Figure 13.15 is an 8-input 2-output combinational circuit (en and op are assumed to be generated by equations (13.19)). As this circuit belongs to the critical path (p.Tcomb.circuit in (13.22)), instead of a 4-bit adder and a 4-input 2-output combinational circuit (Figure 13.15), alternative options are an 8-input 2-output optimized logic circuit, generated with Boolean minimization techniques, or an 8-input 2-output look-up table. If the most signi cant bits

In the past this investment has shown a relatively moderate range of price fluctuations relative to other investments This investment may experience larger or smaller price declines or price increases depending on market conditions Some of this risk may be offset by owning other investments with different portfolio makeups or investment strategies

The delays at the I/O of the FPGA are minimized. More logic is available internally. Superior clock-to-out timing. Superior setup timing.

s0 (n 1) and c0 (n 1) are not used (Comment 6.4), the combinational circuit has 6 inputs and 2 outputs. 13.2.3.3 FPGA Implementation of the Carry-Save SRT-2 Divider A FPGA implementation of the binary SRT divider cell of Figure 13.16 is shown in Figure 13.17.

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